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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Name: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Brand: Springer International Publishing AG
SKU: 02076816
Price: 105.09 EUR
Availability: InStock
Author: Brandon Noia
ISBN: 9783319023779

Brandon Noia

Krishnendu Chakrabarty

Language

English

Book Hardback

Libristo code: 02076816

Publishers Springer International Publishing AG, November 2013

This book describes innovative techniques to address the testing needs of 3D stacked integrated circ... Full description

Libristo code: 02076816

257 b

105.09 € VAT included

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This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.