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SATH: Simulated Annealing C code To FPGA Hardware compiler

Name: SATH: Simulated Annealing C code To FPGA Hardware compiler
Brand: VDM Verlag Dr. Müller
SKU: 06824904
Price: 49.99 EUR
Availability: InStock
Author: Jonathan Phillips
ISBN: 9783639165128

Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler

Jonathan Phillips

Language

English

Book Paperback

Libristo code: 06824904

Publishers VDM Verlag Dr. Müller, November 2008

A tool flow is presented for deriving accelerator§circuits on an FPGA §from ANSI C source code by ex... Full description

Libristo code: 06824904

122 b

49.99 € VAT included

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A tool flow is presented for deriving accelerator§circuits on an FPGA §from ANSI C source code by exploring architecture§solutions that §conform to a preset template through scheduling and§mapping §algorithms. A case study carried out on simulated§annealing-based §scheduling software used for spacecraft systems is§explained. The goal §of the tool is the derivation of a design that§maximizes throughput §while minimizing footprint. Results obtained are§compared with a peer §C to RTL tool, a space-borne embedded processor and a§commodity§desktop processor for a variety of problems.