Check order status

Become part of a community of book lovers from all over the world and get access to a whole bunch of benefits. Create an account for free

Austrian Post 5.49 € GLS courier 4.99 € DPD courier 4.49 € DPD point 3.49 €

Contact

How to shop

Help

My account

▸ Empty :-(

Design and Implementation of FPGA based 64 bit MAC Unit

Name: Design and Implementation of FPGA based 64 bit MAC Unit
Brand: LAP Lambert Academic Publishing
SKU: 17964002
Price: 31.69 EUR
Availability: InStock
Author: Siva Nagendra Reddy P.
ISBN: 9783330345997

Siva Nagendra Reddy P.

Language

English

Book Paperback

Libristo code: 17964002

Publishers LAP Lambert Academic Publishing, November 2016

Nowadays in VLSI, the technology size, power, and speed are the main constraints to design any circu... Full description

Libristo code: 17964002

78 b

31.69 € VAT included

In stock at our supplier Shipping in 5-8 days

Delivery to Austria

Up to 30 days for returns

Customers also purchased

mondo di colore. Cry Babies Emanuela Brumana

Paperback

10.29 €

Az emberiség történelme térképeken - Bővitett kiadás

Hardback

51.19 €

Ca ira mieux demain Michel Drucker

Paperback

9.49 €

ipotesi neocattolica. Politologia dei movimenti anti-gender Massimo Prearo

Book

16.59 €

S.O.S. forêt en détresse marie Colot

Paperback

17.99 €

EEnVV Sueman Cil

Paperback

12.95 €

Relaciones Interpersonales en el Preescolar Melba Hernández

Paperback

182.29 €

Histoire de la Terreur 1792-1794. T. Troisieme (Ed.1862-1881) Mortimer Ternaux

Paperback

35.29 €

Unbestimmte Schuldfähigkeitsfeststellungen Anja Schiemann

Paperback

44.90 €

Nowadays in VLSI, the technology size, power, and speed are the main constraints to design any circuits. In normal multipliers, delay will be more and the number of computations also will be more. Because of that speed of the circuits designed with the normal multipliers will be low and it will consume more power. This book describes Multiply and Accumulate Unit using Vedic Multiplier and DKG reversible logic gates. The Vedic Multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic to perform high speed operations. Reversible logic gates are also the essential constraint for the promising field of Quantum computing. The Urdhava Triyagbhayam multiplier is used for the multiplication function to reduce partial products in the multiplication process and to get high concert and less area. The reversible logic is used to get less power. The MAC is designed using Verilog code, simulation, synthesis is done in both RTL compiler using Xilinx and implemented on Spartan 3e FPGA Board.