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Chaos-based cryptography on FPGA
English
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IoT devices we use every day are becoming interconnected entities across the planet. They comprise autonomous embedded sensory objects that are resource-constrained in terms of computing capabilities, energy, and memory capacities. Moreover, these devices can be affected by various security threats. This requires the design of new cryptographic methods that are efficient in terms of security, time overhead, and energy consumption. To address these challenges, particularly in terms of security, chaos-based cryptographic primitives have been developed in this thesis. First, we implemented and evaluated the statistical security and hardware metrics of certain chaotic maps on the FPGA board. Then, we designed, implemented, and analyzed four secure PRNGs-CS and their corresponding stream ciphers. Finally, we designed, implemented, and evaluated the performance of a new chaos-based encryption/decryption architecture. The experimental results demonstrate the high degree of security and the good hardware metrics achieved by the proposed chaotic systems, making them suitable for securing sensitive data.
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