Contact
How to shop
Delivery
Shopping guide
Pipelined Multi-core MIPS Machine
Hardware Implementation and Correctness Proof
English
132 b
Delivery to Austria
Up to 30 days for returns
Customers also purchased
/
Paperback
37.19
€
/
Paperback
52.95
€
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.§The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.§Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.
About the book
English
Categories
Give this book today
It's easy
1 Add to cart and choose Deliver as present at the checkout 2 We'll send you a voucher 3 The book will arrive at the recipient's addressYou might also be interested in
/
Hardback
78.29
€
/
Paperback
55.79
€
Hi! I'm Libroamiko, your book advisor.
How can I help you?